The present invention relates to a charge pump which is to be installed in a PLL circuit, and, more particularly, to a charge pump which quickly locks its frequency to a desired frequency and maintain a stable frequency output signal.
FIG. 1 is a schematic block diagram of a conventional PLL circuit 10. The PLL circuit 10 has a phase comparator 11, a charge pump 12, a low-pass filter (LPF) 13, a voltage controlled oscillator (VCO) 14 and a frequency divider 15. The phase comparator 11 provides the charge pump 12 with first and second phase difference signals UP and DN which have pulse widths according to a phase difference between a reference signal RIN having a predetermined frequency and a frequency-divided signal FIN from the frequency divider 15. The charge pump 12 sends the LPF 13 an output signal Co which varies in accordance with the pulse widths of the first and second phase difference signals UP and DN. The LPF 13 smoothes the output signal Co from the charge pump 12 and supplies a DC voltage signal Lo to the VCO 14. The VCO 14 sends an external circuit an oscillation output signal Fout having a frequency according to the voltage value of the DC voltage signal Lo. The VCO 14 also sends the oscillation output signal Fout to the frequency divider 15. The frequency divider 15 frequency divides the oscillation output signal Fout and sends the resultant frequency-divided signal FIN to the phase comparator 11. The PLL circuit 10 operates such that the frequency of the oscillation output signal Fout output from the VCO 14 substantially matches, or is locked to a desired frequency.
FIG. 4 is a circuit diagram of the phase comparator 11. The phase comparator 11 has four or first to fourth D flip-flops (DFs) 21 to 24, and exclusive OR (EOR) gates 25 and 26. The phase comparator 11 operates according to the timing charts illustrated in FIGS. 5 to 7. FIG. 5 shows an example where the rising of the reference signal RIN coincides with the rising of the frequency-divided signal FIN. In this case, since the phase of the reference signal RIN substantially coincides with the phase of the frequency-divided signal FIN, the phase comparator 11 outputs the first and second phase difference signals UP and DN which have the same pulse width. FIG. 6 shows an example where the rising of the reference signal RIN comes later than the rising of the frequency-divided signal FIN. In this case, the phase of the frequency-divided signal FIN leads the phase of the reference signal RIN, and the phase comparator 11 outputs the first phase difference signal UP whose pulse width is narrower than that of the second phase difference signal DN. FIG. 7 depicts an example where the rising of the reference signal RIN comes earlier than the rising of the frequency-divided signal FIN. In this case, the phase of the reference signal RIN leads the phase of the frequency-divided signal FIN, and the phase comparator 11 outputs the first phase difference signal UP whose pulse width is wider than that of the second phase difference signal DN.
As shown in FIG. 2, the charge pump 12 includes a P channel MOS (PMOS) transistor TP1 and an N channel MOS (NMOS) transistor TN1 connected in series between a first power supply line L1 connected to a high-potential voltage supply V.sub.DD and a second power supply line L2 connected to a low-potential voltage supply V.sub.SS. The PMOS transistor TP1 has a source which is supplied with the voltage of the high-potential voltage supply V.sub.DD, a drain connected to the drain of the NMOS transistor TN1 and a gate to which the first phase difference signal UP is input. The NMOS transistor TN1 has a source which is supplied with the voltage of the low-potential voltage supply V.sub.SS and a gate which is supplied with the second phase difference signal DN. A node N1 between the drains of the transistors TP1 and TN1 serves as a terminal for outputting the output signal Co from the charge pump 12.
As the PMOS transistor TP1 is turned on in response to the first phase difference signal UP of an L level, the charge pump 12 performs a charge operation to let the current flow to the LPF 13 to increase the amount of charge in the LPF 13. The LPF 13, which includes a resistor and a capacitor, raises the voltage of the output signal Lo with an increase in the amount of charge. That is, the charge pump 12 carries out the charge operation in a period where the first phase difference signal UP has an L level.
As the NMOS transistor TN1 is turned on in response to the second phase difference signal DN of an H level, the charge pump 12 performs a discharge operation to drain the current from the LPF 13, which reduces the amount of charge stored in the LPF 13. The LPF 13 decreases the voltage of the output signal Lo in accordance with a decrease in the amount of charge. That is, the charge pump 12 carries out the discharge operation in a period where the second phase difference signal DN has an H level.
In the example of FIG. 5, as the phase comparator 11 outputs the first and second phase difference signals UP and DN which have the same pulse width, the charge pump 12 carries out a charge operation (pumping out the current I (Co) (positive side)) and a discharge operation (pumping up the current I (Co) (negative side)) for the same period of time. As shown in FIG. 8(a), therefore, the voltage V (Lo) of the output signal Lo of the LPF 13 does not vary and the VCO 14 holds the frequency of the output signal Fout.
In the example of FIG. 7, as the phase comparator 11 outputs the first phase difference signal UP which has a wider pulse width than the second phase difference signal DN, the charge pump 12 carries out a longer charge operation than a discharge operation. In other words, the charge pump 12 executes pumping-out of the current I (Co) (positive side) longer than pumping-up of the current I (Co) (negative side). As shown in FIG. 8(b), therefore, the voltage V (Lo) of the output signal Lo of the LPF 13 rises and the VCO 14 increases the frequency of the output signal Fout.
In the example of FIG. 6, as the phase comparator 11 outputs the first phase difference signal UP which has a narrower pulse width than the second phase difference signal DN, the charge pump 12 performs a shorter charge operation than a discharge operation. That is, the charge pump 12 executes pumping-up of the current I (Co) (negative side) longer than pumping-out of the current I (Co) (positive side). As shown in FIG. 8(c), therefore, the voltage V (Lo) of the output signal Lo of the LPF 13 drops, causing the VCO 14 to decrease the frequency of the output signal Fout.
Referring to FIG. 3, an equivalent circuit of the charge pump 12 is shown as first and second resistors R1 and R2 connected in series between the first and second power supply lines L1 and L2. A voltage difference between the voltage of the high-potential voltage supply V.sub.DD and the voltage of the low-potential voltage supply V.sub.SS is constant. Therefore, when the potential at the node N1 is high and increased close to the voltage of the high-potential voltage supply V.sub.DD for example, a potential difference across the first resistor R1 becomes smaller than a potential difference across the second resistor R2. When the potential at the node N1 is low and decreased close to the voltage of the low-potential voltage supply V.sub.SS, a potential difference across the first resistor R1 becomes larger than a potential difference across the second resistor R2.
The potential differences across the first and second resistors R1 and R2 are the source-drain potential differences of the transistors TP1 and TN1, respectively. Thus, each transistor TP1 or TN1 has a greater drive performance as the source-drain potential difference becomes larger, and has a smaller drive performance as the source-drain potential difference becomes smaller. In a greater drive performance, a large current flows in the transistor, whereas with a smaller drive performance, little current flows in the transistor. The drive performances of the individual transistors TP1 and TN1 have the following influences on the operation of the PLL circuit 10.
When the potential at the node N1 is high and increased close to the voltage of the high-potential voltage supply V.sub.DD, as the drive performance of the NMOS transistor TN1 is greater than that of the PMOS transistor TP1, more current flows in the NMOS transistor TN1 than the PMOS transistor TP1 even when the first and second phase difference signals UP and DN are input. Consequently, the charge amount gets larger than the discharge amount.
FIG. 9 shows, in a matrix form, the ratios of the charge amount by the PMOS transistor TP1 to the discharge amount by the NMOS transistor TN1 based on the relationship between the voltage V(N1) at the node N1 and the phase difference between the reference signal RIN and the frequency-divided signal FIN. In FIG. 9, the ratios are given by numerals above the waveforms. In the case of the center portion in FIG. 9 (where the phases of both signals RIN and FIN substantially coincide with each other and the voltage V(N1) at the node N1 is set near the midway between the voltage of the high-potential voltage supply V.sub.DD and the voltage of the low-potential voltage supply V.sub.SS), for example, the ratio of the charge amount to the discharge amount is 4:4.
In the case of the lower center portion in FIG. 9 (where both signals RIN and FIN are substantially in phase with each other and the voltage at the node N1 is high), a large current flows in the NMOS transistor TN1 so that the ratio of the charge amount to the discharge amount is 2:6. In this case, the voltage V (Lo) of the output signal Lo of the LPF 13 drops and the frequency of the oscillation output signal Fout from the VCO 14 is decreases. This leads to a malfunction where the oscillation output signal Fout of the PLL circuit 10 is unlocked. That is, the oscillation output signal Fout of the PLL circuit 10 decreases even though the reference signal RIN is substantially in phase with the frequency-divided signal FIN and the frequencies of both signals are substantially the same.
In the lower left case in FIG. 9, where the phase of the frequency-divided signal FIN lags behind the phase of the reference signal RIN and the voltage at the node N1 is high, a large current flows in the NMOS transistor TN1, increasing the discharge amount, so that the ratio of the charge amount to the discharge amount becomes 3:3. In this case, the LPF 13 outputs the output signal Lo having a constant voltage V(Lo). The VCO 14 sends out the oscillation output signal Fout having a constant frequency in response to the output signal Lo of the LPF 13. As a result, the frequency of the oscillation output signal Fout does not vary regardless of the delayed phase of the frequency-divided signal FIN. In other words, while the voltage at the node N1 is held high, the oscillation output signal Fout with a constant frequency is output.
In the lower right case in FIG. 9, where the phase of the frequency-divided signal FIN leads the phase of the reference signal RIN and the voltage at the node N1 is high, the discharge amount increases so that the ratio of the charge amount to the discharge amount becomes 1:9. In this case, the LPF 13 drastically drops the voltage V(Lo) of the output signal Lo. The VCO 14 sharply decreases the frequency of the oscillation output signal Fout in response to the output signal Lo of the LPF 13. Consequently, the frequency of the oscillation output signal Fout overshoots (undershoots) the desired frequency, increasing the lockup time of the oscillation output signal Fout.
In the upper left case in FIG. 9, where the phase of the frequency-divided signal FIN lags behind the phase of the reference signal RIN and the voltage at the node N1 is low, the charge amount increases so that the ratio of the charge amount to the discharge amount becomes 9:1. In this case, the VCO 14 rapidly increases the frequency of the oscillation output signal Fout in response to the output signal Lo of the LPF 13. As a result, the lockup time of the PLL circuit increases.
In the upper right case in FIG. 9, where the phase of the frequency-divided signal FIN leads the phase of the reference signal RIN and the voltage at the node N1 is low, the charge amount increases so that the ratio of the charge amount to the discharge amount becomes 3:3. In this case, the VCO 14 sends out the oscillation output signal Fout having a constant frequency in response to the output signal Lo of the LPF 13. Consequently, the frequency of the oscillation output signal Fout is not locked to a predetermined frequency.
FIG. 10 is a schematic block diagram of a conventional phase comparator 30 which has been improved with respect to the above problem. The phase comparator 30 has nine or first through ninth NAND gates 30a to 30i. The second and third NAND gates 30b and 30c form a first flip-flop 31, and the fourth and fifth NAND gates 30d and 30e form a second flip-flop 32.
When the phase of the frequency-divided signal FIN lags behind the phase of the reference signal RIN, as shown in FIG. 11(a), the phase comparator 30 outputs the first phase difference signal UP whose pulse width corresponds to the phase difference and the second phase difference signal DN having a predetermined level. The second phase difference signal DN is inverted by an inverter circuit (not shown) and is then applied to the gate of the NMOS transistor TN1 of the charge pump 12. The charge pump 12 carries out only a charge operation in response to the first and second phase difference signals UP and DN.
When the phase of the frequency-divided signal FIN leads the phase of the reference signal RIN, as shown in FIG. 11(b), the phase comparator 30 outputs the second phase difference signal DN whose pulse width corresponds to the phase difference and the first phase difference signal UP having a predetermined level. The charge pump 12 carries out only a discharge operation in response to the first and second phase difference signals UP and DN.
When the reference signal RIN is substantially in phase with the frequency-divided signal FIN, the phase comparator 30 outputs the first and second phase difference signals UP and DN having a predetermined level. As the charge pump 12 does not perform a charge/discharge operation in response to the first and second phase difference signals UP and DN having the predetermined level, the voltage of the output signal from the charge pump 12 is kept constant, as shown in FIG. 12. This keeps the frequency of the oscillation output signal Fout constant so that the oscillation output signal Fout is locked.
When the voltage V(N1) at the node N1 is high, however, the drive performance of the PMOS transistor TP1 decreases, reducing the charge amount. Consequently, the charge operation of the charge pump 12 becomes slower and the speed of the voltage rise of the output signal Lo of the LPF 13 gets slower. As a result, the frequency of the oscillation output signal Fout from the VCO 14 is slightly increased. This slow charge operation elongates the lockup time of the oscillation output signal Fout.
Accordingly, it is an object of present invention to provide a charge pump having a decreased lock time while improving the frequency stability.